1. Field of the Invention
The present invention relates to an accumulating multiplication circuit, and more specifically to an accumulating multiplication circuit having a function of executing a double-precision multiplication at a high speed.
2. Description of Related Art
A conventional accumulating multiplication circuit is basically constituted of a multiplication part and an arithmetical operation part, and operates as follows: The multiplication part receives two items of data of for example "n" bits, and outputs data of "2n" bits. The arithmetical operation part receives the data of "2n" bits outputted by the multiplication part and another data of "2n" bits, and outputs data of "2n" bits.
By using this conventional accumulating multiplication circuit, a multiplication of "2n" bits.times."2n" bits expressed in the 2'complement, that is, a double-precision multiplication will be executed as follows:
Here, supposing that a multiplicand and a multiplier are A and B, respectively, in the case of executing the multiplication of two numbers of "2n" bits, expressed in the 2'complement, the multiplicand and the multiplier can be expressed in the following formulas: ##EQU1##
Supposing that a product of A and B is P, P is shown by the following formula: ##EQU2##
Here, supposing that Q,R,S and T are expressed by the formulas (6) to (9), respectively, P can be shown by the following formula (10): ##EQU3##
Thus, the double-precision multiplication of "2n" bits can be executed by executing the following four kinds of single-precision multiplication and also executing the shift and addition for weighting of 2.sup.-2n or 2.sup.-n in accordance with the formula (10).
Q.multidot.R: 2'complement.times.2'complement PA1 Q.multidot.T: 2'complement.times.Absolute value PA1 S.multidot.R: Absolute value.times.2'complement PA1 S.multidot.T: Absolute value.times.Absolute value PA1 first to four registers for holding the most significant "n" bits of a multiplier, where "n" is a positive integer, the least significant "n" bits of the multiplier, the most significant "n" bits of a multiplicand, and the least significant "n" bits of the multiplicand, respectively, PA1 a first multiplexor for selecting either an output data of the first register or an output data of the second register, so as to supply the selected output data, PA1 a Booth's decoder receiving the selected output data outputted from the first multiplexor, PA1 a second multiplexor for selecting either an output data of the third register or an output data of the fourth register, so as to supply the selected output data, PA1 a partial product generating circuit receiving an output of the Booth's decoder and an output of the second multiplexor, for generating partial product, and PA1 a partial product adder circuit receiving the partial product from the partial product generating circuit. PA1 fifth and sixth registers for respectively holding the most significant "n" bits and the least significant "n" bits of data used for the arithmetical operation with the product generated in the multiplication part PA1 a third multiplexor having a first input receiving the "2n" bit-data held in the fifth and sixth registers, a second input receiving 0 and a third input, PA1 a shifter receiving an output data of the third multiplexor for shifting the received data rightward by "n" bits, PA1 a fourth multiplexor selecting either the output data of the third multiplexor or an output data of the shifter 31 so as to supply the selected data, PA1 an arithmetical operation circuit receiving an output of the fourth multiplexor and an output of the partial product adder circuit, for outputting a "2n-bit" output data which is a result of the operation, an output of the arithmetical operation circuit being supplied to the third input of the third multiplexor, and PA1 seventh and eighth registers respectively receiving and holding the most significant "n" bits and the least significant "n" bits of the "2n-bit" output data outputted from the arithmetical operation circuit.
In this case, the total number of the operations is six in the whole, that is, one accumulating multiplication of a 2'complement.times.a 2'complement, two accumulating multiplications of a 2'complement.times.an absolute value, one multiplication of an absolute value.times.an absolute value and two n-bit shifts. Namely, the required operation time is six times longer than that of the single-precision operation.
As mentioned above, in the case of executing a double-precision operation to obtain the operation results of "2n" bits, the conventional accumulating multiplication circuit as mentioned above requires the operation time six times as long as that of the single-precision multiplication. Further, it requires two times of saving of data carried over by the shifting in order to obtain the operation result of "4n" bits.